1. Technical Field
The present disclosure relates to the multiplication of a clock and, more particularly, to clock multipliers and methods of multiplying a clock without accumulating a frequency/phase difference between an input clock and an output clock when the multiplying ratio is increased.
2. Discussion of Related Art
Generally, a clock multiplier in an integrated circuit generates internal clocks used in the integrated circuit by multiplying a frequency of an input clock. That is, even though the integrated circuit receives an input clock having a lower frequency, the clock multiplier causes the integrated circuit to be capable of operating at a higher frequency.
A clock multiplier typically includes a phase locked loop (PLL) or a delay-locked loop (DLL).
FIG. 1 is a block diagram illustrating a conventional clock multiplier using a phase locked loop.
Referring to FIG. 1, a clock multiplier 100 using a phase locked loop may include a phase/frequency detector 110, a pump 120, a loop filter 130, a voltage-controlled oscillator 140, and a divider 150.
The clock multiplier 100 generates an output clock FOUT by controlling a control voltage VCON provided to the voltage-controlled oscillator 140. The output clock FOUT has a frequency that is generated by multiplying a frequency of an input clock FIN by N. For controlling the control voltage VCON, the clock multiplier 100 may include the phase/frequency detector 110, the pump 120, the loop filter 130, and a divider 150.
The phase/frequency detector 110 receives two clocks and detects a frequency/phase difference between the two received clocks. When a frequency/phase difference exists, the phase/frequency detector 110 adjusts the control voltage VCON by generating a first control signal, for example, UP, or a second control signal, for example, DN.
For example, the phase/frequency detector 110 may receive the input clock FIN and a divided clock FOUT/N corresponding to a clock that is generated by dividing a frequency of the output clock FOUT by N and may detect a frequency/phase difference between the input clock FIN and the divided clock FOUT/N. When a frequency of the divided clock FOUT/N is lower than that of the input clock FIN, the phase/frequency detector 110 may generate the first control signal, for example, UP. When the frequency of the divided clock FOUT/N is higher than that of the input clock FIN, the phase/frequency detector 110 may generate the second control signal, for example, DN.
The pump 120 generates a current for increasing or decreasing an amount of a charge of the loop filter 130 based on the first control signal and the second control signal. For example, when the first control signal is received, the pump 120 may increase the amount of the charge of the loop filter 130. When the second control signal is received, the pump 120 may decrease the amount of the charge of the loop filter 130.
The loop filter 130 generates the control voltage VCON based on the amount of the charge adjusted by the pump 120. For example, when the pump 120 increases the amount of the charge of the loop filter 130, the loop filter 130 may increase the control voltage VCON. When the pump 120 decreases the amount of the charge of the loop filter 130, the loop filter 130 may decrease the control voltage VCON.
The voltage-controlled oscillator 140 adjusts the frequency of the output clock FOUT based on the control voltage VCON. For example, the frequency of the output clock FOUT outputted from the voltage-controlled oscillator 140 may correspond to a frequency that is generated by multiplying the frequency of the input clock FIN by N.
The divider 150 divides the frequency of the output clock FOUT by N, and provides the phase/frequency detector 110 with the divided clock FOUT/N.
As described above, the clock multiplier 100 may generate the output clock FOUT having the desired frequency by multiplying the frequency of the input clock FIN by N using the phase locked loop.
The clock multiplier 100 using the phase locked loop, however, requires a specific time for adjusting the frequency/phase difference between the input clock FIN and the divided clock FOUT/N. In addition, when the frequency of the output clock FOUT does not correspond to the frequency obtained by multiplying the frequency of the input clock FIN by N, an error of the clock multiplier 100 may be accumulated until the error is corrected with respect to a next input clock FIN.
FIG. 2 is a block diagram illustrating a conventional clock multiplier using a delay-locked loop.
Referring to FIG. 2, a clock multiplier 200 using a delay-locked loop may include a phase/frequency detector 210, a pump 220, a loop filter 230, a voltage-controlled delay line 240, and an edge combiner 250.
The phase/frequency detector 210 receives two clocks and detects a frequency/phase difference between the two received clocks. When the frequency/phase difference exists, the phase/frequency detector 210 adjusts the control voltage VCON by generating a first control signal, for example, UP, or a second control signal, for example, DN.
For example, the phase/frequency detector 210 may receive the input clock FIN and a delayed clock DIN corresponding to a clock that is generated by delaying the input clock FIN by N times, and may detect a frequency/phase difference between the input clock FIN and the delayed clock DIN. When a frequency of the delayed clock DIN is lower than that of the input clock FIN, the phase/frequency detector 210 may generate the first control signal, for example, UP. When the frequency of the delayed clock DIN is higher than that of the input clock FIN, the phase/frequency detector 210 may generate the second control signal, for example, DN.
The pump 220 generates a current for increasing or decreasing an amount of a charge of the loop filter 230 based on the first control signal and the second control signal. For example, when the first control signal is received, the pump 220 may increase the amount of the charge of the loop filter 230. When the second control signal is received, the pump 220 may decrease the amount of the charge of the loop filter 230.
The loop filter 230 generates the control voltage VCON based on the amount of the charge adjusted by the pump 220. For example, when the pump 220 increases the amount of the charge of the loop filter 230, the loop filter 230 may increase the control voltage VCON. When the pump 220 decreases the amount of the charge of the loop filter 230, the loop filter 230 may decrease the control voltage VCON.
The voltage-controlled delay line 240 generates N delayed clocks by adjusting a delay of the input clock FIN based on the control voltage VCON. For example, when the control voltage VCON is increased, the voltage-controlled delay line 240 may decrease the delay of the input clock FIN and may generate the N delayed clocks. When the control voltage VCON is decreased, the voltage-controlled delay line 240 may increase the delay of the input clock FIN and may generate the N delayed clocks.
The edge combiner 250 receives the N delayed clocks outputted from the voltage-controlled delay line 240 and generates an output clock FOUT having a frequency obtained by multiplying the frequency of the input clock FIN by N based on the N delayed clocks.
As described above, the clock multiplier 200 may generate the output clock FOUT having the desired frequency by multiplying the frequency of the input clock FIN by N using the delay-locked loop.
The clock multiplier 200 using the delay-locked loop, however, has a problem that the phase/frequency difference between the delayed clocks is increased in accordance with increasing a multiplying ratio. That is, the clock multiplier 200 using the delay-locked loop may accumulate an error of the phase/frequency difference between the delayed clocks.
Therefore, despite increasing the multiplying ratio, a clock multiplier that does not accumulate the phase/frequency difference between the input clock and the output clock is required.